<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Architectures on Werner Strydom</title><link>https://wernerstrydom.com/lab/architectures/</link><description>Recent content in Architectures on Werner Strydom</description><generator>Hugo</generator><language>en-us</language><atom:link href="https://wernerstrydom.com/lab/architectures/index.xml" rel="self" type="application/rss+xml"/><item><title>SPARC</title><link>https://wernerstrydom.com/lab/architectures/sparc/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/sparc/</guid><description>Sun Microsystems&amp;rsquo; RISC architecture, introduced in 1987 and 64-bit since the V9 specification. Oracle and Fujitsu built its last server generations; Solaris is its native operating system.</description></item><item><title>POWER and PowerPC</title><link>https://wernerstrydom.com/lab/architectures/power/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/power/</guid><description>IBM&amp;rsquo;s RISC lineage. POWER built servers and supercomputers; PowerPC, its 1991 offshoot with Apple and Motorola, spent a decade in every Macintosh and lives on in embedded systems.</description></item><item><title>RISC-V</title><link>https://wernerstrydom.com/lab/architectures/riscv/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/riscv/</guid><description>An open, royalty-free instruction set from UC Berkeley, published in the 2010s. Anyone may implement it, and everyone does — from fifty-cent microcontrollers to server-class processors.</description></item><item><title>MIPS</title><link>https://wernerstrydom.com/lab/architectures/mips/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/mips/</guid><description>One of the first commercial RISC architectures, out of Stanford in the mid-eighties. It powered SGI workstations and nineties game consoles, and survives mostly in networking silicon.</description></item><item><title>Arm</title><link>https://wernerstrydom.com/lab/architectures/arm/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/arm/</guid><description>The most widely shipped instruction set there is, from Acorn roots in 1980s Cambridge. arm64 is its 64-bit architecture — phones, single-board computers, Apple silicon, and a growing share of servers.</description></item><item><title>x86-64</title><link>https://wernerstrydom.com/lab/architectures/x86/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/x86/</guid><description>AMD&amp;rsquo;s 64-bit extension of Intel&amp;rsquo;s x86, first shipped in 2003 and since then the default architecture of desktops, laptops, and servers.</description></item><item><title>Xtensa</title><link>https://wernerstrydom.com/lab/architectures/xtensa/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/xtensa/</guid><description>Tensilica&amp;rsquo;s configurable embedded architecture, best known as the core inside Espressif&amp;rsquo;s ESP32 Wi-Fi microcontrollers.</description></item><item><title>FPGA</title><link>https://wernerstrydom.com/lab/architectures/fpga/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://wernerstrydom.com/lab/architectures/fpga/</guid><description>Not an instruction set at all: programmable logic you configure into whatever hardware you need — including processors that never shipped as silicon.</description></item></channel></rss>