RISC-V

RISC-V began as a Berkeley research project around 2010 and became the first instruction set to go genuinely open: the specification is royalty-free, stewarded by RISC-V International, and anyone may build an implementation without a license. The design is a small base ISA plus optional extensions — multiplication, atomics, floating point, compressed instructions — which is how the same architecture spans microcontrollers and server processors.

That openness has a cost measured in device trees: extensions keep arriving and each SoC needs its own kernel support, so how close a board sits to the mainline kernel matters as much as its specification. The usual way in is QEMU and the GNU toolchain on a machine you already own; real silicon earns its place when emulation stops answering the question.

In this family

• riscv64 — RV64, the Linux-capable line.
• riscv32 — RV32, the microcontroller line.

In the lab

• Microchip PolarFire SoC Icicle Kit fpga · in use RISC-V cores next to FPGA fabric on one die.
• SiFive HiFive Unmatched sbc · in use · discontinued A RISC-V development board built around the Freedom U740.
• SiFive HiFive1 Rev B mcu · in use An RV32 microcontroller board built around the FE310.